1. Field of the Invention
The present disclosure relates to a semiconductor device, a semiconductor device structure, a method of forming a semiconductor device and a method of forming a semiconductor device structure. Particularly, the present disclosure relates to FinFET device structures having gate structures with ferroelectric high-k materials and non-ferroelectric high-k materials.
2. Description of the Related Art
In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. In particular, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes significantly smaller than 1 μm, the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 100 nm or less. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs may be made much smaller than any discreet circuit composed of separate independent circuit components. Indeed, the majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors or MOSFETs, occasionally also simply referred to as MOS transistors, and passive elements, such as resistors, e.g., diffusion resistors, and capacitors, integrated on a semiconductor substrate within a given surface area. Typical present-day ICs involve millions of single circuit elements formed on a semiconductor substrate.
The basic function of a MOSFET is that of an electronic switching element, controlling a current through a channel region provided between two junction regions which are referred to as source and drain. The control of the conductivity state of the channel region is achieved by means of a gate electrode being disposed over the channel region and to which gate electrode a voltage relative to source and drain is applied. In common planar MOSFETs, the channel region extends in a plane between source and drain. Generally, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of the channel is changed and switching between a conducting state or “ON-state” and a non-conducting state or “OFF-state” may be achieved. It is important to note that the characteristic voltage level at which the conductivity state changes (usually called the “threshold voltage”), therefore, characterizes the switching behavior of the MOSFET, and it is generally an issue to keep variations in the threshold voltage level low when implementing a desired switching characteristic. However, with the threshold voltage depending nontrivially on the transistor's properties, e.g., materials, dimensions, etc., the implementation of a desired threshold voltage value during fabrication processes involves careful adjustment and fine tuning during the fabrication processes, which makes the fabrication of complex semiconductor devices by advanced technologies more and more difficult.
In general, it was observed that, with the sizes of individual MOSFETs having steadily decreased over the last decades, strongly scaled MOSFETs suffered more and more from undesirable effects once the length of the channel of a MOSFET entered the same order of magnitude as the width of the depletion layer of source and drain. For strongly scaled MOSFETs, for example, the OFF-state leakage current (i.e., the leakage current in the OFF-state) increased with the idle power required by the device. Accordingly, these deteriorating effects, which appear at small scales and are associated with a short channel length, are frequently referred to as so-called “short channel effects.” In order to continue to lower scales, tremendous efforts are needed to address the issues or marginalities, variabilities and challenges appearing in scaling towards VLSI (very large scale integration) MOSFET technologies at, for instance, 20 nm or less, such that all the marginalities in each individual process step and all variabilities are properly addressed and, at best, reduced.
In the efforts of overcoming the above-described issues encountered when reaching smaller and smaller scales, multi-gate MOSFET devices have been proposed. A kind of multi-gate MOSFET device used for advanced 22/14 nm technologies is realized as a so-called “FinFET.” In general, FinFETs represent three-dimensional transistors formed by thin fins extending upwardly from a semiconductor substrate, where particularly the transistor channel is three-dimensional. For example, in some designs of FinFET devices, the channel is formed along the vertical sidewalls of the fin (which is also referred to as a “double-gate transistor”) or along the vertical sidewall surfaces and the upper horizontal surface of the fin (leading to so-called “tri-gate transistors”). Double-gate transistors and tri-gate transistors have wide channels and, on the other hand, high performance, which may be achieved without substantially increasing the area of the substrate surface required by these transistors because a transistor's performance, being measured by its transconductance, is proportional to the width of the transistor channel. Therefore, by the multi-gate configuration as provided by the three-dimensional channel of FinFETs, these semiconductor devices allow for a better control of the channel region when compared to common planar transistor devices.
Furthermore, due to the various efforts that were carried out to improve memory arrays, ferroelectric gate field effect transistors (FeFETs) have been recently in the focus of research. In general, ferroelectric materials have dielectric crystals which show a spontaneous electric polarization similar to ferromagnetic materials having a spontaneous magnetization. Upon applying an appropriate external electric field to a ferroelectric material, the direction of polarization of the ferroelectric material may be reoriented. The basic idea is to use the direction of spontaneous polarization in ferroelectric memories for storing digital bits. In FeFETs, the effect that one makes use of is the possibility to adjust the polarization state of a ferroelectric material on the basis of appropriate electrical fields which are applied to the ferroelectric material which, in a FeFET, is usually the gate oxide. Since the polarization state of a ferroelectric material is preserved unless it is exposed to a high, with regard to the polarization state, counter oriented electrical field or a high temperature, it is possible to “program” a capacitor formed of ferroelectric material such that an induced polarization state reflects an information unit. Therefore, an induced polarization state is preserved, even upon removing an accordingly “programmed” device from a power supply. In this way, FeFETs allow the implementation of non-volatile electrically switchable data storage devices.
On the basis of ferroelectric materials, it is possible to provide non-volatile memory devices, particularly random excess memory devices similar in construction to DRAM devices, but differing in that a ferroelectric layer is used instead of a dielectric layer such that a non-volatile memory device is obtained. For example, the 1T-1C storage cell design in a FeRAM is similar in construction to the storage cell in widely used DRAM in that both cell types include one capacitor and one excess transistor—a linear dielectric is used in a DRAM cell capacitor, whereas in a FeRAM cell capacitor the dielectric structure includes a ferroelectric material. Other types of FeRAMs are realized as 1T storage cells which consist of a single FeFET employing a ferroelectric dielectric instead of the gate dielectric of common MOSFETs. The current-voltage characteristic between source and drain of a FeFET depends in general on the electric polarization of the ferroelectric dielectric, i.e., the FeFET is in the on or off state, depending on the orientation of the electric polarization state of the ferroelectric dielectric. Writing on a FeFET is achieved in applying a writing voltage to the gate relative to source, while a 1T-FeRAM is read out by measuring the current when applying a reading voltage to source and drain. It is noted that reading out of a 1T-FeRAM is nondestructive.
Although a FeFET or a ferroelectric capacitor represent in theory very promising concepts for complex semiconductor devices, it is a difficult task to identify appropriate ferroelectric materials which are compatible with existing advanced manufacturing processes of complex devices, particularly at very small scales. For example, commonly known ferroelectric materials, such as PZT or perovskites, are not compatible with standard CMOS processes. According to present understanding, hafnium (Hf) based materials, which are used in current fabrication technologies, exhibit a para-electric behavior due to the predominantly monoclinic crystal structure present in hafnium oxide. However, recent research results indicate that dielectric materials on the basis of hafnium oxide may represent promising candidates for materials with ferroelectric behavior to be used in the fabrication of ferroelectric semiconductor devices. It is, for example, known that the monoclinic structure may be suppressed in hafnium oxide materials doped with Zr, Si, Y or Al, wherein the crystal structures of ferroelectric nature may be stabilized.
In embedding FeFETs together with standard MOSFETs into existing process flows according to advanced CMOS techniques, ferroelectric semiconductor devices and non-ferroelectric semiconductor devices having different gate stack heights due to the height difference between the ferroelectric gate dielectric and the non-ferroelectric gate dielectric are formed. Especially in FinFET integration schemes, strong topographical differences appear after the gate formation between FeFET and MOSFET devices, causing problems in replacement gate processes, particularly at chemical mechanical polishing (CMP) steps.
It is, therefore, desirable to provide a semiconductor device that does not increase topography differences due to a ferroelectric gate dielectric. It is further desirable to provide a method of forming an according semiconductor device. Furthermore, it is desirable to provide a semiconductor device structure having ferroelectric and non-ferroelectric semiconductor devices which do not show strong topography variations. It is further desirable to provide a method of forming an according semiconductor device structure.